1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a column address decoder and decoding method for controlling a column select line enable time.
2. Description of the Related Art
Generally, to read data from or write data to a particular memory cell of a semiconductor memory device, the memory cell is addressed by a row address and a column address. In a semiconductor memory device such as a dynamic random access memory (DRAM), an address externally applied together with a write command or a read command is decoded to select a row address and a column address. Generally, to select a column address a column select line (CSL) is used. Data is written after decoding a column address and CSL is enabled upon arrival of the data to be written. When data is read, a row address strobe (RAS) to a column address strobe (CAS) delay time (tRCD) is used for enabling the CSL. The column address decoder is equally divided into a pre-decoder and a main decoder.
FIG. 1 shows a conventional column address pre-decoder of a semiconductor memory device. Referring to FIG. 1, the conventional column address pre-decoder has inverters 100 and 105, and a first through a fourth decoding units 120 through 150. Each decoding unit 120 through 150 has a structure in which NAND gates and inverters are serially connected. Column addresses (CAi, CAj) applied to the inverters 100 and 105 are CMOS-level signals obtained by synchronizing buffered external addresses to a clock signal. A CSL enable signal (PCSLEP) is generated internally in the DRAM for enabling a CSL when a lower bit column address is input. A bank signal (PBANK) corresponding to a bank address is generated when a bank is selected and used to enable a CSL when a higher bit column address is input. Also, pre-decoded column addresses (DCAij, DCAijB, DCAiBj, DCAiBjB) are generated by combining the column addresses (CAi, CAj). Here, i and j represent the numbers of column addresses, and have a value inclusive of and between 0 and N.
The conventional column address pre-decoder shown in FIG. 1 decodes an input signal of a combination of the column addresses (CAi, CAj) or a combination of two or more column addresses, and combines a CSL enable signal (PCSLEP) or a bank signal (PBANK) to the decoded signal to generate a pre-decoded column address (DCAij through DCAiBjB).
FIGS. 2 and 3 are timing diagrams for explaining the operation of the circuit shown in FIG. 1. FIG. 2 shows normal operation, while FIG. 3 shows abnormal operation.
Referring to FIG. 2, pre-decoded column addresses (DCAiBjB, DCAiBj) of (d) and (e) of FIG. 2 are enabled in response to a CSL enable signal (PCSLEP), while column select lines (CSLi, CSLj) of (f) and (g) of FIG. 2 are enabled in response to the pre-decoded column addresses (DCAiBjB, DCAiBj). As shown in FIG. 2, the enable time for the column select lines (CSLi, CSLj) is typically determined only by a CSL enable signal (PCSLEP). In the conventional technology, a CSL enable signal (PCSLEP) is delayed or advanced so that a CSL is enabled at the right time. As can be seen in the Figure, column addresses (CAi, CAj) are enabled when a CSL enable signal (PCSLEP) is low. At low operation speeds, even though a time for generating a CSL enable signal (PCSLEP) is adjusted, the operation can be efficient because column addresses (CAi, CAj) are enabled only when a CSL enable signal (PCSLEP) is low. At high operation speeds, an abnormal operation can occur.
Referring to FIG. 3, when a memory device operates at a high frequency, glitch components 32 and 34 can occur because column addresses (CAi, CAj) are enabled when a CSL enable signal (PCSLEP) is high. The higher the operational frequency and the greater the memory capacity, the longer the path for data to be written to a memory cell and the greater the data line loads. Therefore, the glitch components 32 and 34 can occur in the column select lines (CSLi, CSLj), shown in (e) and (g) of FIG. 3, and cause abnormal operations. As memory capacity and operation speeds increase, clock cycle times (tCC) decrease and it becomes increasingly difficult for the conventional decoding method to coordinate the data input and CSL enable signal. Therefore, a new method that can efficiently enable a CSL for a data input time is needed.
FIGS. 4 and 5 are circuit diagrams of column select line enable circuits disclosed in the U.S. Pat. No. 5,835,441. Referring to FIGS. 4 and 5, the column select line enable circuits coordinate a CSL enablement by using a separation switch 43 and a latch 44. The circuit in FIG. 5 implements a coupling circuit 46 shown in FIG. 4 with an AND gate, and a pre-charge transistor 47 is added to set a latch input, which is different from the circuit in FIG. 4. However, CSL enable circuits of FIGS. 4 and 5 adjust a CSL enable time not from a column address pre-decoder, but in a data path from a column decoder 40 to a column select unit 48. When circuits of FIGS. 4 and 5 are compared to the circuit of FIG. 1, it is seen that the enablement is adjusted only by the CSL enable signal (PCSLEP) in FIG. 1, but in FIGS. 4 and 5, CSL enablement is adjusted by a separation signal (ISO) applied to the separation switch 43 and an enable signal (ENABLE). As a result, the conventional CSL enable circuits shown in FIGS. 4 and 5 are more complex.
To solve the above problems, it is an object of the present invention to provide a column address decoder of a semiconductor memory device capable of stably enabling a column select line by a simple control signal regardless of the length of a data line. According to an aspect of the invention, a column address decoder of a semiconductor memory device is provided for decoding column addresses to enable a corresponding column select line, the column address decoder comprising a column address pre-decoder for latching combinations of the column addresses when a column select line enable signal is in a first level, and outputting the latched result as pre-decoded column addresses when the column select line enable signal is in a second level and a column address main decoder for combining the pre-decoded column addresses and enabling the corresponding column select line among a plurality of column address select lines.
According to another aspect of the invention, a column address decoding method is provided for decoding column addresses to enable the corresponding column select line, the column address decoding method comprising: determining whether or not a column select line enable signal is in a first level, and if in a first level, latching the combination of the column addresses; determining whether or not the input column address is a lower bit addresses; if the input column addresses are lower bit addresses, combining the latched result with the column select line enable signal and then outputting the combined signal as a pre-decoded column address; if the input column addresses are higher bit addresses, determining whether or not the column select line enable signal is in a second level; and if the column select line enable is in a second level, outputting the latched result as the pre-decoded column address.
According to a preferred embodiment of the invention, a semiconductor memory device is provide which comprises a column address pre-decoder adapted to latch combinations of column addresses when a column select line enable signal is in a first level, and outputting the latched result as pre-decoded column addresses when the column select line enable signal is in a second level; a column address main decoder adapted to decode the pre-decoded column addresses and outputting the decoded result; and a column select line select circuit adapted to enable the corresponding column select line among a plurality of column select lines in response to the decoded result of the column address main decoder.